r&s®smw-九游官网下载

• slowdown of complete signal generation process (incl. baseband signal generation, digital iq output speed, awgn and mimo/fading simulation)
• output of up to 4 digital iq streams simultaneously and up to 8 digital iq streams in multiplex mode
• support for all important signal generator functions (including mimo) allows using exactly the same stimulus for testing early prototypes and testing the later design
• asynchronous digital iq output supported
• control of signal generation speed by dut
• use of r&s^®ex-iq-box for interface adaptation to dut

to shorten the time-to-market for chipsets or modules, it is important to verify the design as soon as possible during the development process. hence it is desired to test hardware prototypes against realistic physical signals already at a very early r&d stage.

hardware prototypes or simulated hardware (by means of hw emulators or fpga test boards) typically act like a speed-wise scaled-down representation of the final chip or module design. the typical stimulus for accessing the behavior of such a prototype is a digital iq signal which also has to be scaled down accordingly in terms of timing, sample rate and bandwidth.

the r&s^®smw-k551 option allows slowing down of the whole digital signal generation process of the r&s^®smw200a (incl. baseband signal generation, digital iq output speed, awgn and mimo/fading simulation). it enables the r&d engineer to evaluate the general functionality and the algorithms of early hardware prototypes via digital interfaces – without the need for a completely finished design.